Semiconductor devices employing trench structures are well known in the art. FIG. 1 is a simplified schematic cross-sectional view of prior art N-channel trench metal oxide semiconductor device 100 employing a trench structure for the control gate. Device 100 comprises N+ substrate 110, of for example single crystal silicon, which acts as the drain of device 100 and on which is provided drain contact 112 and drain connection 114. N layer 120 is formed on substrate 110, usually by epitaxy. In an active region 170 of device 100, P-body regions 130 are provided extending from surface 132 into N layer 120. N+ source regions 134 are provided extending from surface 132 into P-body regions 130.
A gate structure is formed in a trench, which extends into device 100 from surface 132 through P-body region 130 and into N layer 120. The trench is generally centered between source regions 134. Portion 122 of N layer 120 beneath the gate structure acts as the drift space of device 100. Gate oxide 152 is formed on the exposed interior surface of the trench, and a conductive gate electrode 154 is provided substantially filling the trench. Contacts 136 are provided on source regions 134 (and portions of P-body regions 130), and the contacts 136 are coupled to source connection 138. Contact 156 is provided on gate electrode 154 and coupled to gate connection 158. When appropriate bias is applied, source-drain current 160 flows from source regions 134 through N-channel regions 140 in P-body regions 130 and through N drift space portion 122 of layer 120 to substrate 110 which, as indicated above, acts as the drain of device 100.
In an edge region 180 of device 100, a P-edge region 182 is provided in order to avoid breakdown in the edge region 180. The P-edge region 182 extends from surface 132 into N layer 120 to a depth that is greater than the depth of the P-body regions 130. During manufacture of device 100, the P-edge region 182 is formed using conventional masking and implant processes, which are distinct from the masking and implant processes used to produce the P-body regions 130.
Although the P-edge region 182 is generally sufficient to avoid breakdown in the edge region 180, the inclusion of P-edge region 182 may have several disadvantages. For example, distinct masking and implantation steps are used to form the P-edge region 182, and the mask used during formation of the P-edge region 182 may cause semiconductor surface roughness. In addition, the P-edge implant may cause latent damage and weakness in the semiconductor, thus potentially resulting in defects that may increase the occurrence of substantial gate-to-source leakage current (e.g., IGSS failures) in the edge region 180 of the device 100. In addition, P-edge regions (not shown) in adjacent terminations may cause parasitic device (PMOS) and potential source-to-source leakage. Further, formation of the P-edge region 182 may add approximately 10 to 15 percent of extra cost to the fabrication process for device 100.
Accordingly, there is an ongoing need for improved device structures, materials and methods of fabrication that can overcome these difficulties and provide improved performance. It is further desirable that the methods, materials, and structures employed be compatible with present day manufacturing capabilities and materials and not require substantial modifications to available manufacturing procedures or substantial increases in manufacturing costs. Furthermore, other desirable features and characteristics of the various embodiments will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.